1. Field of the Invention
The present invention relates to a static semiconductor memory device, and in particular, to a static semiconductor memory having a plurality of memory cells each of which includes a driving transistor formed of a bulk type MOS transistor and a load formed of a thin film transistor.
2. Description of Related Art
Referring to FIG. 1A, there is shown an equivalent circuit of one memory cell in a typical static semiconductor memory device in the prior art.
The memory cell shown in FIG. 1A includes a first inverter circuit composed of a P channel thin film transistor T.sub.1 and an N channel MOS transistor T.sub.2, and a second inverter circuit composed of a P channel thin film transistor T.sub.3 and an N channel MOS transistor T.sub.4. A flip flop is composed of a cross conjunction of these two inverter circuits, and the flipflop constitutes one memory cell. Data of "1" or "0" can be memorized in memory nodes N.sub.1 and N.sub.2 of this memory cell.
N channel MOS transistor T.sub.5 and T.sub.6 are provided as a transmission gate used to write data to the memory cell and to read data from the memory cell. A gate electrode of each of these MOS transistors is connected to a word line W.sub.L, and one of source/drain regions of each of these MOS transistors is connected to a corresponding bit line B.sub.L, and the other source/drain region is connected to the corresponding memory node N.sub.1 or N.sub.2 of the memory cell.
With a recent improved integration density, the load transistor (transistor T.sub.1, T.sub.3 in FIG. 1A) of each of the pair of inverters constituting each one flipflop, is composed of a P channel thin film transistor, which is in turn located above a bulk type N channel MOS transistor (transistor T.sub.2, T.sub.4 of FIG. 1A) which forms the driving transistor of the inverter.
Referring to FIG. 2, there is shown a diagrammatic layout pattern of the above mentioned memory cell circuit in a semiconductor integrated circuit device.
In FIG. 2, N.sup.+ type impurity regions 1a, 1b and 1c are selectively formed at a surface region of a P-type semiconductor substrate (not shown) made of for example silicon. These N.sup.+ type impurity regions 1a, 1b and 1c constitute respective source/drain regions of the transistors T.sub.6 and T.sub.4 of FIG. 1A. In addition, N.sup.+ type impurity regions 1d, 1e and 1f are also selectively formed at the surface region of the same P-type semiconductor substrate so as to respective constitute source/drain regions of the transistors T.sub.5 and T.sub.2.
Respective gate electrodes 2a and 2b of the transistors T.sub.4 and T.sub.2 are formed of a first level polysilicon film, and word lines 3a and 3b are also formed of the first level polysilicon film. Here, the word lines 3a and 3b also functions as a gate electrode of the transistor T.sub.6 and T.sub.5, respectively.
Ground wirings 4a and 4b are formed of a second level polysilicon layer which is formed at a level higher than the first second level polysilicon layer. These ground wirings 4a and 4b are interconnected through through-holes 5a and 5b to the N.sup.+ diffusion layers 1c and 1f, respectively. Respective gate electrodes 6a and 6b of the P channel thin film transistors (transistor T.sub.1, T.sub.3 in FIG. 1A) are formed of a third level polysilicon film which is formed at a level higher than the second second level polysilicon layer. The gate electrode 6a is connected to both of the gate electrode 2b and the N.sup.+ type diffusion layer 1b through a through-hole 7a. The gate electrode 6b is connected to both of the gate electrode 2a and N.sup.+ type diffusion layer 1e through a through-hole 7b.
Fourth level polysilicon film 8c and 8d, which are formed at a level higher than the third second level polysilicon layer, constitute a channel region and source/drain regions of the P channel thin film transistor and also constitute a Vcc wiring. The polysilicon film 8c is connected to the gate electrode 6b of the thin film transistor by a through-hole 9a, and similarly, the polysilicon film 8d is connected to the gate electrode 6a of the thin film transistor by a through-hole 9b.
Being not drawn, a through-hole for connecting with a bit line (not shown) is formed on each of the N.sup.+ type diffusion layers 1a and 1d.
Now, the P channel thin film transistor of the prior art will be explained in detail with reference to FIGS. 3A and 3B. FIG. 3A shows a thin film transistor part extracted from FIG. 2, and FIG. 3B is a cross-sectional view taken along the line A--A in FIG. 2.
A polysilicon film 80 formed of the fourth level polysilicon film is located above the gate electrode 60 formed of the third level polysilicon film through an insulation layer 100 interposed therebetween. The polysilicon film 80 is divided into a source region 80a which also functions as the Vcc wiring, a drain region 80b and a channel region 80c. The source region 80a is a P type high impurity density region, and the drain region 80b is composed of a P type high impurity region 80b.sub.1 and a P type low impurity density region 80b.sub.2. These regions are formed by an ion implantation of boron.
As shown in FIG. 3, the high impurity density region 80b.sub.1 of the drain region is formed apart from the gate electrode 60. This is principally for the purpose of lowering a leak current in an off condition.
In the prior art static semiconductor memory device constructed as mentioned above, with advance in microminiaturization of the device size, it has become susceptible to a soft error in which data is inverted by .alpha.-ray radiated from a package and a wiring material.
The soft error will occur in the following manner: In FIG. 1A, it is now assumed that the memory node N.sub.1 is at a high level ("1") and the memory node N.sub.2 is at a low level ("0") (in this case, the N.sup.+ type diffusion layer 1e is at a high level and the N.sup.+ type diffusion layer 1b is at a low level). In this state, when .alpha.-ray is injected into the memory, electron-hole pairs are created, and the electrons created are collected into the N.sup.+ diffusion layer 1e. Consequently, the electric potential of the memory node N.sub.1 drops, so that the N channel MOS transistor T.sub.4 turns OFF and the P channel thin film transistor T.sub.3 turns ON. Therefore, the electric potential of the memory node N.sub.2 rises up. As the result, the N channel MOS transistor T.sub.2 turns ON, and the P channel thin film transistor T.sub.1 turns OFF. Accordingly, the memory is put into a new and different stable state.
As a method for improving the soft error immunity in this type static semiconductor memory device, it has been proposed to lower the impurity density of the gate electrodes 6a and 6b of the thin film transistors so as to make higher its sheet resistance (Proc. IEICE fall conf. '91, C-427, P5-141, "Improvement Of Soft Error Immunity in a Polysilicon PMOS Load Memory Cell"). In this case, to make higher the sheet resistance of the gate electrodes 6a and 6b which were ordinarily injected with phosphorus of the amount of 1.times.10.sup.19 to 1.times.10.sup.20 atoms/cm.sup.3 in the prior art, it is necessary to lower the amount of injection of phosphorus to 1.times.10.sup.17 to 1.times.10.sup.19 atoms/cm.sup.3.
This equivalently results in that a resistor R.sub.1 is connected between respective gates of the transistor T.sub.1 and T.sub.2, and another resistor R.sub.2 is connected between respective gates of the transistor T.sub.3 and T.sub.4, as shown in FIG. 1B. In FIG. 1B, element corresponding to those shown in FIG. 1A are given the same Reference Numerals, and explanation thereof will be omitted.
In the semiconductor memory device applied with the above mentioned counterplan as shown in FIG. 1B, the resistance between the memory node N.sub.1 and the gate of the thin film transistor T.sub.3 and the resistance between the memory node N.sub.2 and the gate of the thin film transistor T.sub.1 are increased, with the result that the circuit time constant for charging the gate electrode of each thin film transistor increases. Therefore, even if the electric potential of the memory node N.sub.1 which was at a high level would be lowered by the injection of electrons generated by the .alpha.-ray, the drop of the electric potential of the gate electrode of the thin film transistor T.sub.3 is delayed. Accordingly, even if the .alpha.-ray is irradiated, the transistor T.sub.3 does not immediately turn ON, and therefore, the memory node N.sub.1 keeps a low electric potential for some time. As a result, the thin film transistor T.sub.1 continues to keep its ON state and the MOS transistor T.sub.2 continues to keep its OFF state, and in a short time, the electric potential of the memory node N.sub.1 recovers the high level. Accordingly, the soft error immunity is ameliorated in the improved semiconductor memory device mentioned above.
In the prior art static semiconductor memory device applied with the .alpha.-ray immunity mentioned above, the injection amount of phosphorus into the gate electrode of the thin film resistor is reduced to a degree of 1.times.10.sup.17 to 1.times.10.sup.19 atoms/cm.sup.3. In this case, however, a great dispersion of the sheet resistance occurs dependently upon inevitable variations in the manufacturing condition. In addition, it may happen sometimes that a sufficiently large resistance cannot be gained. In such a case, a good soft error immunity cannot be gained.
Furthermore, a sufficient effect of soft error immunity cannot be obtained by the prior art counterplan. Even though a great sheet resistance could be obtained, the .alpha.-ray immunity would become insufficient in the case that the microminiaturization of semiconductor memory devices is further advanced.